Common clock counter

ALTERNATIVE – COUNTER WITH COMMON CLOCK

• We can avoid the illegal state by detecting the last legal state (eg., 5 in a modulo 6 counter), and then set to 0 on next clock pulse.
• This requires a non-cascading counter.
• We need a common clock
• Lets build it up from 1 to 3 bits …..

MOD 6 COUNTER WITH COMMON CLOCK

• First a 1 bit counter
• 1-bit (counts 0...1...0...1...)
• Set J and K to make it toggle

This circuit will use a common clock

2-BIT COUNTER

• 2-bit (counts 00...01...10...11...00...)
• Connect Q1 to J2 and K2
• Now Q2 only changes state if Q1 is set (halves the frequency).
• but there is no Co (when state = 11)
• Because we have a common clock.

3-BIT COUNTER

• 3-bit? Add another Flip-flop?
• Doesn't work. Q3 is not just supposed to flash at half frequency of Q2
• Think about the truth table.

COUNTING WITH 3 BITS (LITTLE-ENDIAN)

The issue is that the gates are all using the same clock, so Q3 will

toggle at 3, and then the counter will reset to 0. Try it, You will get the number sequence: 0, 1, 2, 7, 0...

Decimal Q1 Q2 Q3 Q3 (actual)

(expected)

0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 1
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 1

THE FIX... 3-BIT COUNTER

• Add an AND gate to only toggle Q3 when both Q1 and Q2 are set. That's our Carry Out (Co).

NOW TO RESET WHEN IT GETS TO 6 (ILLEGAL STATE)...

• When the output is 110 (Q1=0, Q2=1, Q3=1), use a 2-input AND gate to trigger the Reset on all of the Flip-Flops.

ISSUES

• Currently the illegal state (6) still momentarily occurs
• Solution:
• add D-Flip-Flops as a buffer before displaying
• Adds a delay of 1 clock pulse

SUMMARY

• Common clock counter synchronises FF state transitions
• One clock to rule them all!
• Requires explicit logic gates check FF transitions
• Not quite as elegant as ripple counters!
• D FFs can buffer output for a clock pulse:
• Allow circuit to stabilise
• illegal state cannot “escape”

` push

RESOURCES

• Video tutorials:
• A quick reminder that I am progressively making video tutorials for *some* key topics.
• Not all will be covered, but I try to give practical and quick walk throughs of circuit designs (and later, ASM code)
• They are linked from the lab sheets.
• Discussion board

pop

SHIFT REGISTERS

A shift register takes input from one end, and at each clock change this value is moved to the next D-Flip-Flop. This is used in serial data transfer when a byte (say) of data sent on a cable one bit after another can be collected in a series of D Flip-Flops to rebuild the whole data byte. This is called serial-to-parallel conversion. Parallel output

Q Q Q Serial Output Input D D D Q Q Q

Clock Clock Clock

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SHIFT REGISTERS

Here is how a high A B C travels through a 3 bit Q Q Q Output shift register. For this Input D D D example we assume Q Q Q that each of the shift register bits is cleared at Clock Clock Clock the start.

Clock

Input

FF A

Q outputs FF B

FF C

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SHIFT LEFT SHIFT REGISTERS

• The shift registers shown so far shift data to the right. A simple rewiring gives a shift register that can move data left. Of course these may also have the ability to parallel load. Q1 Q2 Q3 Serial in

D in D in D in

FF1 FF2 FF3

Serial clock

Parallel clock // in // in // in

1 2 3

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LETS BUILD ONE!

WHAT DOES A SHIFT REGISTER DO?

• Moves a state (number such as 0, 1) from a low order bit to a higher order bit.
• Multiplies a (binary) number by two.
• Number of "shifts" depends on number of clock cycles.
• Can use a counter to enable/disable clock, thereby programming the amount of shift.
• Can shift in the other direction – divide numbers by 2.
• Can have two clocks – one for left-shift, one for right- shift, or use gates to determine the shift direction.
• Can be used as 1-bit of a stack (push/pop).

A SIMPLE SHIFT REGISTER FROM D FLIP-FLOPS

SI

little-endian

• Same circuit as a decimal counter, but only input 1 pulse instead of holding Input (Data) high. Only does serial to parallel.
• To shift n bits, input n clock cycles. 22

LEFT-SHIFT (LOW BIT TO HIGH BIT) SERIAL TO PARALLEL

• Can modulate the Input (serial input) to load states into a register (serial to parallel conversion)
• Once the "conversion" is complete, disable the clock and store in a latch/register.

little-endian

PARALLEL LOAD SHIFT REGISTERS

• Some shift registers allow all flip-flops to load at once,
• i.e. in parallel.
• This gives parallel-to-serial conversion

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RIGHT-SHIFT SERIAL OR PARALLEL INPUT: 4-BIT

Parallel Output

• Flip-flops are connected (output to input) with a common clock to cascade input from high bytes to low bytes.
• Each flip-flop has a parallel bit OR-ed to the input to allow PReset. 25

WHAT ABOUT BI-DIRECTIONAL SHIFTING (SELECTABLE)?

• This takes some thinking!
• You need a pin to select which direction
• You need to allow inputs to any D Flip Flop to come from either direction
• Try and design a 2 bit selectable direction Shift Register!
• Serial input only
• You will probably need some OR gates,AND gates, and a NOT gate

THE LOGISIM SHIFT REGISTER

THINGS TO TRY

• Parallel Load a value and Shift to see it halve.
• Implement both directions and see it double or halve.
• Hold down SI to inject a bit – see it halve or double.

WHERE ARE WE?

Fast memory (RAM) Persistent

• program and data memory (Disks) Counter

Central processing Mother Programmable unit (CPU) board shift register registers IP

Screen memory ALU within Keyboard the CPU Input / Output accel

29 Channels cards Mouse

THINGS TO REMEMBER (FILL THIS IN)

ALU Types of Flip Inputs Clock type Extra Circuit Elements Component Flops (Gates)

Register Required state Common clock (n-bit latch) Ripple none Counter Decimal D Flip Flops Counter Mod n Cascading clock AND gate Counter Mod 6 Common clock Counter 3-bit counter Enable AND gate Shift Register AND, OR gates to

Things to try

• Enable or disable a clock pulse with a switch.
• Convert the little-endian circuits to big endian.
• Convert the big-endian circuits to little endian.
• Wire up counters to count up or count down depending on the wiring (selectable).
• Control the selection with a flip-flop.
• Up-down counters where an up counter triggers an RS (or JK) flip-flop to enable the up wiring, and the down button unsets the RS flip-flop and enables the down wiring.

IN THE LAB...

• Build a register out of D-Flip-Flops
• Build various counters
• Build a shift register