Counters and Shift Registers

Building a computer? Things we need:

memory within Fast memory (RAM) Persistent the CPU – program and data memory

= banks (Disks)

of flip- flops Instruction Pointer Central processing Motherboard (counter) unit (CPU) registers IP full adder + Screen shift ALU operations Keyboard

Input / Output accel

2 Channels cards Mouse

REGISTERS

Fast RAM (uses transistor states)

• Uses clocked flip-flops
• Inside the CPU chip
• Limited number of them (cause it's hardware)
• Let's build one...

D-TYPE FLIP-FLOP

• Set data to high – Q goes high on next clock pulse. Stays high.
• Set presets Q to high when pulled high
• Reset clears Q when pulled high

• In Logisim we can also leave PR' and CLR' disconnected.

D-FLIP-FLOPS AS A REGISTER OR LATCH

A register (many bits) or latch (usually one bit) can be made Input before the clock Information 1 0 1 1 up from a series of D-Flip-Flops latched driven by a common clock. now D D D D

The transfer from the D side to the Clock Q Q Q Q Q side for all D flip flops occurs 1 0 1 1 simultaneously as this clock Output after the clock changes. This arrangement is found in CPU registers http://www.electronics-tutorials.ws/sequential/seq_4.html

6 COS10004 Computer Systems 6

8 BIT REGISTER

little-endian

Little Endian

BIG ENDIAN AND LITTLE ENDIAN DATA FORMAT

• Technical definition for the order of bytes:
• Big Endian:
• The most signficant byte resides in the smallest memory address
• Little Endian:
• The least significant byte resides in the smallest memory address

BIT ENDIANNESS

• Bits generally don’t have an address, so definitions refer to the positional order of bits
• Big Endian:
• The most significant bit comes first
• Little Endian:
• The least significant bit comes first
• This matters for interpreting the value of a bit string (especially if bits are received as a serial stream!)
• Eg What is 1011 in decimal?
• 1110 (Big endian), or 1310 (Little endian) 9

8 BIT REGISTER

little-endian

Little Endian

Big Endian

SUMMARY

• D Flip Flops generally form the building blocks of registers
• Registers:
• Allow us to store bit strings that represent data
• Reside close to the CPU, allowing fast and easy access
• Bit Endianness determines how we interpret bit strings:
• Big Endian: most significant bit comes first
• Little Endian: least significant bit comes first
• Next Lecture: ripple counters with JK Flip Flops

Dr Chris McCarthy

COUNTERS IN DIGITAL LOGIC

• A circuit that stores and increments the number of occurrences of an event:
• Most commonly clock pulses
• Two types we will consider:
• Asynchronous (ripple) counter
• Synchronous (common clock) counter
• J-K Flip Flops central to both

RIPPLE COUNTER

• Ripple counters utilise the toggle setting of J-K Flip Flops:
• Consider this circuit
• What happens to Qo each clock pulse?:

• Ripple counters utilise the toggle setting of J-K Flip Flops:
• Consider this circuit
• What happens to Qo each clock pulse?:

• Ripple counters utilise the toggle setting of J-K Flip Flops:
• Consider two Flip Flops:
• What happens to Qo and Q1 each clock pulse?

• Ripple counters utilise the toggle setting of J-K Flip Flops:
• Consider two Flip Flops:
• What happens to Qo and Q1 each clock pulse?

• Ripple counters utilise the toggle setting of J-K Flip Flops:
• What about three FFs?
• What happens to Q0, Q1, and Q2 each clock pulse?

• Ripple counters utilise the toggle setting of J-K Flip Flops:
• Consider this circuit:
• What happens to Qo, Q1 and Q3 each clock pulse?

• Ripple counters utilise the toggle setting of J-K Flip Flops:
• And finally, four FFS
• : Q0, Q1, Q2, Q3?

• Ripple counters utilise the toggle setting of J-K Flip Flops:
• And finally, four FFS
• : Q0, Q1, Q2, Q3?

One’s

Two’s

Four ’s

Eight’s

RIPPLE COUNTER

• The ripple effect of FF toggles exactly matches binary counts:
• each oscillates at half the frequency of the FF before it!
• The bits stored in the FFs thus represent incrementing binary values
• BUT – on which edge of the clock pulse?

One’s

Two’s

Four ’s

Eight’s

RIPPLE COUNTER

One’s

Two’s

Four ’s

Eight’s

RIPPLE COUNTER

One’s

Two’s

Four ’s

Eight’s

RIPPLE COUNTER

One’s

Two’s

Four ’s

Eight’s

RIPPLE COUNTER

One’s

Two’s

Four ’s

Eight’s

RIPPLE COUNTER

One’s

Two’s

Four ’s

Eight’s

RIPPLE COUNTER

One’s

Two’s

Four ’s

Eight’s

RIPPLE COUNTER

One’s

Two’s

Four ’s

Eight’s

COUNTING DOWN?

• What if I want to count down instead of up?
• Requires nothing more than a change of FF trigger:
• Change FF to trigger on rising edge of clock pulse
• Lets take a look

SUMMARY

• Ripple counter achieves a simple binary counter
• It utilises the J-K toggle setting:
• J = 1, K = 1,
• It is asynchronous because:
• No common clock
• State changes ripple through from least significant FF
• We can change directionality of counter using FF trigger:
• Falling edge = increment
• Rising edge = decrement

COUNTERS USING J K FLIP-FLOPS

big-endian

• Note: these are negative-triggered JK Flip-Flops – they count up.
• If you use positive-triggered ones, and connect each clock input to the previous Q they count down.
• There are other ways of making a down counter – most rely on using controlled gates to change the wiring between the flip-flops (more later). 23

COUNTERS USING J K FLIP-FLOPS

little-endian

• We can change the interconnections to make a little-endian version
• The Enable and CLR' pins are the same. The connection of each Q to CLK is reversed.

A LEVEL COUNTER?

• Why not? Great for meters, progress displays
• Use D Flip-flops, common clock, Q connected to next D input.
• Increments on each clock pulse as long as D is held high.

DECIMAL COUNTING?

• Count down? Wire up the Q---D connections backwards
• Decrements on each clock pulse as long as D is held low.

HMMM.

• Later, we will need to make a circuit which can go up or down depending on the state of a switch.
• We will use controlled gates to enable or disable individual connections between adjacent flip-flops.
• Alternatively we could use a set of flip-flops with two clocks...
• One for up; one for down.

MORE COUNTERS

• Suppose we want to count in a modulo that is not a neat
• Need 3 flip-flops but change the sequence to be 0,1,2,3,4,5,0 etc. (The states 6 and 7 are never used)
• There are two ways in general to do this: We can hard-wire – Detect the first illegal state (6 in this case) and this... with gates! immediately reset to 0 (don’t wait for the clock) and hope no-one notices.
• Detect the last legal value (5 in this case) and force the next clock pulse to reset us to 0.

MODULO 6 WITH MOMENTARY ILLEGAL STATE

• Lets build it and see

MODULO 6 COUNTER WITH A MOMENTARY ILLEGAL STATE

• Detecting the first illegal state (6 in this case) and immediately resetting to 0 (don’t wait for the clock) by using the asynchronous master reset (MR) or CLR‘
• This circuit uses a cascading clock

MR Q MR Q MR Q3

J 1 J 2 J

K K K or 7 forcing the master resets to clear each F/ 1 1 C 1 C F to zero

C C1 2 3

ALTERNATIVE – COUNTER WITH COMMON CLOCK

• We can avoid the illegal state by detecting the last legal state (eg., 5 in a modulo 6 counter), and then set to 0 on next clock pulse.
• This requires a non-cascading counter.
• We need a common clock
• Lets build it up from 1 to 3 bits …..

MOD 6 COUNTER WITH COMMON CLOCK

• First a 1 bit counter
• 1-bit (counts 0...1...0...1...)
• Set J and K to make it toggle

This circuit will use a common clock

2-BIT COUNTER

• 2-bit (counts 00...01...10...11...00...)
• Connect Q1 to J2 and K2
• Now Q2 only changes state if Q1 is set (halves the frequency).
• but there is no Co (when state = 11)
• Because we have a common clock.

3-BIT COUNTER

• 3-bit? Add another Flip-flop?
• Doesn't work. Q3 is not just supposed to flash at half frequency of Q2
• Think about the truth table.

COUNTING WITH 3 BITS (LITTLE-ENDIAN)

The issue is that the gates are all using the same clock, so Q3 will

toggle at 3, and then the counter will reset to 0. Try it, You will get the number sequence: 0, 1, 2, 7, 0...

Decimal Q1 Q2 Q3 Q3 (actual)

(expected)

0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 1
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 1

THE FIX... 3-BIT COUNTER

• Add an AND gate to only toggle Q3 when both Q1 and Q2 are set. That's our Carry Out (Co).

NOW TO RESET WHEN IT GETS TO 6 (ILLEGAL STATE)...

• When the output is 110 (Q1=0, Q2=1, Q3=1), use a 2-input AND gate to trigger the Reset on all of the Flip-Flops.

LOGISIM TIME – LETS JUST BUILD IT!

ISSUES

• To prevent illegal state, add D-Flip-Flops as a buffer
• only the valid counter states are available for display
• Adds a delay of 1 clock pulse.

` push

RESOURCES

• Video tutorials:
• A quick reminder that I am progressively making video tutorials for *some* key topics.
• Not all will be covered, but I try to give practical and quick walk throughs of circuit designs (and later, ASM code)
• They are linked from the lab sheets.
• Discussion board

pop

SHIFT REGISTERS

A shift register takes input from one end, and at each clock change this value is moved to the next D-Flip-Flop. This is used in serial data transfer when a byte (say) of data sent on a cable one bit after another can be collected in a series of D Flip-Flops to rebuild the whole data byte. This is called serial-to-parallel conversion. Parallel output

Q Q Q Serial Output Input D D D Q Q Q

Clock Clock Clock

46 COS10004 Computer Systems 46

SHIFT REGISTERS

Here is how a high A B C travels through a 3 bit Q Q Q Output shift register. For this Input D D D example we assume Q Q Q that each of the shift register bits is cleared at Clock Clock Clock the start.

Clock

Input

FF A

Q outputs FF B

FF C

47 COS10004 Computer Systems 47

SHIFT LEFT SHIFT REGISTERS

• The shift registers shown so far shift data to the right. A simple rewiring gives a shift register that can move data left. Of course these may also have the ability to parallel load. Q1 Q2 Q3 Serial in

D in D in D in

FF1 FF2 FF3

Serial clock

Parallel clock // in // in // in

1 2 3

48 COS10004 Computer Systems 48

LETS BUILD ONE!

WHAT DOES A SHIFT REGISTER DO?

• Moves a state (number such as 0, 1) from a low order bit to a higher order bit.
• Multiplies a (binary) number by two.
• Number of "shifts" depends on number of clock cycles.
• Can use a counter to enable/disable clock, thereby programming the amount of shift.
• Can shift in the other direction – divide numbers by 2.
• Can have two clocks – one for left-shift, one for right- shift, or use gates to determine the shift direction.
• Can be used as 1-bit of a stack (push/pop).

A SIMPLE SHIFT REGISTER FROM D FLIP-FLOPS

SI

little-endian

• Same circuit as a decimal counter, but only input 1 pulse instead of holding Input (Data) high. Only does serial to parallel.
• To shift n bits, input n clock cycles. 51

LEFT-SHIFT (LOW BIT TO HIGH BIT) SERIAL TO PARALLEL

• Can modulate the Input (serial input) to load states into a register (serial to parallel conversion)
• Once the "conversion" is complete, disable the clock and store in a latch/register.

little-endian

PARALLEL LOAD SHIFT REGISTERS

• Some shift registers allow all flip-flops to load at once,
• i.e. in parallel.
• This gives parallel-to-serial conversion

53 COS10004 Computer Systems 53

RIGHT-SHIFT SERIAL OR PARALLEL INPUT: 4-BIT

Parallel Output

• Flip-flops are connected (output to input) with a common clock to cascade input from high bytes to low bytes.
• Each flip-flop has a parallel bit OR-ed to the input to allow PReset. 54

WHAT ABOUT BI-DIRECTIONAL SHIFTING (SELECTABLE)?

• This takes some thinking!
• You need a pin to select which direction
• You need to allow inputs to any D Flip Flop to come from either direction
• Try and design a 2 bit selectable direction Shift Register!
• Serial input only
• You will probably need some OR gates,AND gates, and a NOT gate

THE LOGISIM SHIFT REGISTER

THINGS TO TRY

• Parallel Load a value and Shift to see it halve.
• Implement both directions and see it double or halve.
• Hold down SI to inject a bit – see it halve or double.

WHERE ARE WE?

Fast memory (RAM) Persistent

• program and data memory (Disks) Counter

Central processing Mother Programmable unit (CPU) board shift register registers IP

Screen memory ALU within Keyboard the CPU Input / Output accel

58 Channels cards Mouse

THINGS TO REMEMBER (FILL THIS IN)

ALU Types of Flip Inputs Clock type Extra Circuit Elements Component Flops (Gates)

Register Required state Common clock (n-bit latch) Ripple none Counter Decimal D Flip Flops Counter Mod n Cascading clock AND gate Counter Mod 6 Common clock Counter 3-bit counter Enable AND gate Shift Register AND, OR gates to

Things to try

• Enable or disable a clock pulse with a switch.
• Convert the little-endian circuits to big endian.
• Convert the big-endian circuits to little endian.
• Wire up counters to count up or count down depending on the wiring (selectable).
• Control the selection with a flip-flop.
• Up-down counters where an up counter triggers an RS (or JK) flip-flop to enable the up wiring, and the down button unsets the RS flip-flop and enables the down wiring.

IN THE LAB...

• Build a register out of D-Flip-Flops
• Build various counters
• Build a shift register

Dr Chris McCarthy

RIPPLE COUNTER

• Ripple counters utilise the toggle setting of J-K Flip Flops:

One’s

Two’s Four’s Eight’s

MORE COUNTERS

• Suppose we want to count up to a power of two? For
• Why 6 you ask?

• Suppose we want to count in a modulo that is not a neat
• Why 6 you ask?

MOD 6 COUNTER

• What do we need to do?
• An incrementing counter
• A forced reset of all Flip Flops to zero when the

MODULO 6 COUNTER

• What do we need to do?
• An incrementing counter: falling edge trigger – easy!
• A forced reset of all Flip Flops to zero when the counter reaches 6: some extra logic gates to monitor things, and trigger a FF reset – not too tricky

• Have a go!
• Detect the illegal state (6)
• Reset the FFs to wrap around to zero

MODULO 6 COUNTER WITH A MOMENTARY ILLEGAL STATE

• Detecting the first illegal state (6 in this case) and immediately resetting to 0 (don’t wait for the clock) by using the asynchronous master reset (MR) or CLR‘
• This circuit uses a cascading clock J K C1 Q1 K C2 Q2 J K C3 Q3 J 1 1 1 C

MR MR MR or 7 forcing the master resets to clear each F/

F to zero

SUMMARY

• detect “illegal state”

• Slight problem though:
• Master reset is asynchronous
• The illegal state momentarily still happens!
• We can do better! ….in fact.. We NEED to do better ….next lecture

Dr Chris McCarthy

ALTERNATIVE – COUNTER WITH COMMON CLOCK

• We can avoid the illegal state by detecting the last legal state (eg., 5 in a modulo 6 counter), and then set to 0 on next clock pulse.
• This requires a non-cascading counter.
• We need a common clock
• Lets build it up from 1 to 3 bits …..

MOD 6 COUNTER WITH COMMON CLOCK

• First a 1 bit counter
• 1-bit (counts 0...1...0...1...)
• Set J and K to make it toggle

This circuit will use a common clock

2-BIT COUNTER

• 2-bit (counts 00...01...10...11...00...)
• Connect Q1 to J2 and K2
• Now Q2 only changes state if Q1 is set (halves the frequency).
• but there is no Co (when state = 11)
• Because we have a common clock.

3-BIT COUNTER

• 3-bit? Add another Flip-flop?
• Doesn't work. Q3 is not just supposed to flash at half frequency of Q2
• Think about the truth table.

COUNTING WITH 3 BITS (LITTLE-ENDIAN)

The issue is that the gates are all using the same clock, so Q3 will

toggle at 3, and then the counter will reset to 0. Try it, You will get the number sequence: 0, 1, 2, 7, 0...

Decimal Q1 Q2 Q3 Q3 (actual)

(expected)

0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 1
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 1

THE FIX... 3-BIT COUNTER

• Add an AND gate to only toggle Q3 when both Q1 and Q2 are set. That's our Carry Out (Co).

NOW TO RESET WHEN IT GETS TO 6 (ILLEGAL STATE)...

• When the output is 110 (Q1=0, Q2=1, Q3=1), use a 2-input AND gate to trigger the Reset on all of the Flip-Flops.

ISSUES

• Currently the illegal state (6) still momentarily occurs
• Solution:
• add D-Flip-Flops as a buffer before displaying
• Adds a delay of 1 clock pulse

SUMMARY

• Common clock counter synchronises FF state transitions
• One clock to rule them all!
• Requires explicit logic gates check FF transitions
• Not quite as elegant as ripple counters!
• D FFs can buffer output for a clock pulse:
• Allow circuit to stabilise
• illegal state cannot “escape”

` push

RESOURCES

• Video tutorials:
• A quick reminder that I am progressively making video tutorials for *some* key topics.
• Not all will be covered, but I try to give practical and quick walk throughs of circuit designs (and later, ASM code)
• They are linked from the lab sheets.
• Discussion board

pop

SHIFT REGISTERS

A shift register takes input from one end, and at each clock change this value is moved to the next D-Flip-Flop. This is used in serial data transfer when a byte (say) of data sent on a cable one bit after another can be collected in a series of D Flip-Flops to rebuild the whole data byte. This is called serial-to-parallel conversion. Parallel output

Q Q Q Serial Output Input D D D Q Q Q

Clock Clock Clock

17 COS10004 Computer Systems 17

SHIFT REGISTERS

Here is how a high A B C travels through a 3 bit Q Q Q Output shift register. For this Input D D D example we assume Q Q Q that each of the shift register bits is cleared at Clock Clock Clock the start.

Clock

Input

FF A

Q outputs FF B

FF C

18 COS10004 Computer Systems 18

SHIFT LEFT SHIFT REGISTERS

• The shift registers shown so far shift data to the right. A simple rewiring gives a shift register that can move data left. Of course these may also have the ability to parallel load. Q1 Q2 Q3 Serial in

D in D in D in

FF1 FF2 FF3

Serial clock

Parallel clock // in // in // in

1 2 3

19 COS10004 Computer Systems 19

LETS BUILD ONE!

WHAT DOES A SHIFT REGISTER DO?

• Moves a state (number such as 0, 1) from a low order bit to a higher order bit.
• Multiplies a (binary) number by two.
• Number of "shifts" depends on number of clock cycles.
• Can use a counter to enable/disable clock, thereby programming the amount of shift.
• Can shift in the other direction – divide numbers by 2.
• Can have two clocks – one for left-shift, one for right- shift, or use gates to determine the shift direction.
• Can be used as 1-bit of a stack (push/pop).

A SIMPLE SHIFT REGISTER FROM D FLIP-FLOPS

SI

little-endian

• Same circuit as a decimal counter, but only input 1 pulse instead of holding Input (Data) high. Only does serial to parallel.
• To shift n bits, input n clock cycles. 22

LEFT-SHIFT (LOW BIT TO HIGH BIT) SERIAL TO PARALLEL

• Can modulate the Input (serial input) to load states into a register (serial to parallel conversion)
• Once the "conversion" is complete, disable the clock and store in a latch/register.

little-endian

PARALLEL LOAD SHIFT REGISTERS

• Some shift registers allow all flip-flops to load at once,
• i.e. in parallel.
• This gives parallel-to-serial conversion

24 COS10004 Computer Systems 24

RIGHT-SHIFT SERIAL OR PARALLEL INPUT: 4-BIT

Parallel Output

• Flip-flops are connected (output to input) with a common clock to cascade input from high bytes to low bytes.
• Each flip-flop has a parallel bit OR-ed to the input to allow PReset. 25

WHAT ABOUT BI-DIRECTIONAL SHIFTING (SELECTABLE)?

• This takes some thinking!
• You need a pin to select which direction
• You need to allow inputs to any D Flip Flop to come from either direction
• Try and design a 2 bit selectable direction Shift Register!
• Serial input only
• You will probably need some OR gates,AND gates, and a NOT gate

THE LOGISIM SHIFT REGISTER

THINGS TO TRY

• Parallel Load a value and Shift to see it halve.
• Implement both directions and see it double or halve.
• Hold down SI to inject a bit – see it halve or double.

WHERE ARE WE?

Fast memory (RAM) Persistent

• program and data memory (Disks) Counter

Central processing Mother Programmable unit (CPU) board shift register registers IP

Screen memory ALU within Keyboard the CPU Input / Output accel

29 Channels cards Mouse

THINGS TO REMEMBER (FILL THIS IN)

ALU Types of Flip Inputs Clock type Extra Circuit Elements Component Flops (Gates)

Register Required state Common clock (n-bit latch) Ripple none Counter Decimal D Flip Flops Counter Mod n Cascading clock AND gate Counter Mod 6 Common clock Counter 3-bit counter Enable AND gate Shift Register AND, OR gates to

Things to try

• Enable or disable a clock pulse with a switch.
• Convert the little-endian circuits to big endian.
• Convert the big-endian circuits to little endian.
• Wire up counters to count up or count down depending on the wiring (selectable).
• Control the selection with a flip-flop.
• Up-down counters where an up counter triggers an RS (or JK) flip-flop to enable the up wiring, and the down button unsets the RS flip-flop and enables the down wiring.

IN THE LAB...

• Build a register out of D-Flip-Flops
• Build various counters
• Build a shift register

Dr Chris McCarthy

SHIFT REGISTERS

A shift register takes input from one end, and at each clock change this value is moved to the next D-Flip-Flop. This is used in serial data transfer when a byte (say) of data sent on a cable one bit after another can be collected in a series of D Flip-Flops to rebuild the whole data byte. This is called serial-to-parallel conversion.

2 COS10004 Computer Systems 2

Here is how a high A B C travels through a 3 bit Q Q Q Output shift register. For this Input D D D example we assume Q Q Q that each of the shift register bits is cleared at Clock Clock Clock the start.

Clock

Input

FF A

Q outputs FF B

FF C

3 COS10004 Computer Systems 3

SHIFT LEFT SHIFT REGISTERS

• The shift registers shown so far shift data to the right. A simple rewiring gives a shift register that can move data left. Of course these may also have the ability to parallel load.

4 COS10004 Computer Systems 4

WHAT DOES A SHIFT REGISTER DO?

• Moves a state (number such as 0, 1) from a low order bit to a higher order bit.
• Multiplies a (binary) number by two.
• Number of "shifts" depends on number of clock cycles.
• Level counter (e.g. volume control)
• Can use a counter to enable/disable clock, thereby programming the amount of shift.
• Can shift in the other direction – divide numbers by 2.
• Can have two clocks – one for left-shift, one for right- shift, or use gates to determine the shift direction.

SERIAL-TO-PARALLEL CONVERSION

• Some shift registers allow all flip-flops to load at once,
• i.e. in parallel.
• This gives parallel-to-serial conversion

6 COS10004 Computer Systems 6

RIGHT-SHIFT SERIAL OR PARALLEL INPUT: 4-BIT

Parallel Output

• Flip-flops are connected (output to input) with a common clock to cascade input from high bytes to low bytes.
• Each flip-flop has a parallel bit OR-ed to the input to allow PReset. 7

WHAT ABOUT BI-DIRECTIONAL SHIFTING (SELECTABLE)?

• This takes some thinking!
• You need a pin to select which direction
• You need to allow inputs to any D Flip Flop to come from either direction
• Try and design a 2 bit selectable direction Shift Register!
• Serial input only
• You will probably need some OR gates,AND gates, and a NOT gate

THE LOGISIM SHIFT REGISTER

(NOT FOR USE IN ASSIGNMENTS!

THINGS TO TRY

• Parallel Load a value and Shift to see it halve.
• Implement both directions and see it double or halve.
• Hold down SI to inject a bit – see it halve or double.

W HERE ARE WE?

Fast memory (RAM) Persistent

• program and data memory (Disks) Counter

Central processing Mother Programmable unit (CPU) board shift register registers IP

Screen memory ALU within Keyboard the CPU Input / Output accel

11 Channels cards Mouse

THINGS TO REMEMBER (FILL THIS IN)

ALU Types of Flip Inputs Clock type Extra Circuit Elements Component Flops (Gates)

Register Required state Common clock (n-bit latch) Ripple none Counter Decimal D Flip Flops Counter Mod n Cascading clock AND gate Counter Mod 6 Common clock Counter 3-bit counter Enable AND gate Shift Register AND, OR gates to

WEEK 3 SUMMARY

• Counters:
• Ripple counter (asynchronous)
• Common clock counters (synchronised)
• Mod 6 counter
• Use logic to detect illegal state and reset FFs
• Use D FFs to buffer output and stabilise
• Shift Registers with connected D FFs
• Extremely useful for multi/div, bit shifting, level setting, serial/parallel data conversion.