Clocked Flip Flops (D, JK and T FFs)

BASICS OF ELECTRONIC STORAGE – CPU REGISTERS

• In a computer the output is determined by current inputs and memory (previous inputs) computed together.

Inputs Combinatorial Outputs

Logic

Memory

CPU needs some way to remember information

FLIP-FLOPS WITH CLOCKED INPUTS

• The two most common clocked Flip-Flops are the D and the JK

Q J Q

D Q K Q

. Clock Clock

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D FLIP FLOP

Q

D Q

Clock

• The D flip-flop has only one input, Q is updated to be the same as D when the clock goes active

J-K FLIP FLOP

J Q

K Q

Clock

The JK flip-flop has two inputs.

It is updated when the clock goes active but how it is updated depends on both the J and K inputs.

D FLIP-FLOP

The external D input (Data) internally generate both an R and an S input. These are complements so never get both being active at once. Hence the true table for D and Q after each clock change to active is DN Q N+1 (N means at the clock, N+1 means after the clock) 0 0 D-FFs are used in computer registers and memories and in counters and 1 1 shift registers

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Exercise

• From the description given in the last slide, convert the NOR-gate RS FF into a D-type FF. Use the rising edge of the Clock for “active”.
• Hint: add a couple of AND gates controlled (oppositely) by D
• Clock the AND gates …

RS Fl

Set

Reset

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Exercise – Solution

• Step 1, Add a couple of AND gates to permit updates of state when the clock ticks over.
• Step 2, Replace R and S with one input (D) and use an inverter to ensure that R is always the opposite of S.

Set

Reset

Exercise

complete the timing diagram below

Data is read Data is read here and here here and here

Clock

Data

Q RESET state Data pulse too SET state short-no change Q of state

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J K FLIP-FLOP

J K FF’s are more flexible and can be used for a number of operations. The JK truth table (remember that N+1 means after the clock) J K Q N+1 A sort of 0 0 Q (No Change) programmable N gate 0 1 0 (Reset) 1 0 1 (Set) 1 1 Q N (Toggle) Note the change

The state when both inputs are active has been turned from a problem state (as it was for an RS flip flop) into something very useful (more on this later).

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• Uses tri-input NAND gates.
• Has a defined state (toggle) when both J and K (equivalent to S and R) are high.
• Waits for the clock before it changes state – can’t be made unstable.

Q ’ is another notation for Q

T FLIP-FLOPS

• The T input just toggles the output.

Note the ‘ notation. Q’ means the same as Q

For inputs, CLR’ == CLR which means:

“pull CLR down to activate”

Making a T from an R S Flip-Flop

• Add a couple of NAND gates controlled by D
• Clock the NAND gates inversely…

Set

What goes

Here? Reset

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Making a T from an R S Flip-Flop

• Add a couple of NAND gates controlled by D
• Clock the NAND gates inversely… We invert the Clock to one NAND gate instead of inverting the Data

Set

Reset

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MORE ON CLOCKED FLIP-FLOPS

• Sometimes it is useful to provide both clocked (synchronous) and non-clocked (asynchronous) inputs.
• When power is applied to a flip flop its state cannot be predicted.
• The asynchronous inputs are used as master reset (MR) or set (MS) inputs and override the clocked inputs if we should try to use one of these at the same time as the clock edge.
• http://wearcam.org/ece385/lectureflipflops/flipflops

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D-FLIP-FLOPS AS A REGISTER OR LATCH

A register (many bits) or latch (usually one bit) can be made Input before the clock Information 1 0 1 1 up from a series of D-Flip-Flops latched driven by a common clock. now D D D D

The transfer from the D side to the Clock Q Q Q Q Q side for all D flip flops occurs 1 0 1 1 simultaneously as this clock Output after the clock changes. This arrangement is found in CPU registers http://www.electronics-tutorials.ws/sequential/seq_4.html

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SHIFT REGISTERS

Here is how a high A B C travels through a 3 bit Q Q Q Output shift register. For this Input D D D example we assume Q Q Q that each of the shift register bits is cleared at Clock Clock Clock the start.

Clock

Input

FF A

Q outputs FF B

FF C

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SHIFT REGISTERS

A shift register takes input from one end, and at each clock change this value is moved to the next D-Flip-Flop. This is used in serial data transfer when a byte (say) of data sent on a cable one bit after another can be collected in a series of D Flip-Flops to rebuild the whole data byte. This is called serial-to-parallel conversion. Parallel output

Q Q Q Serial Output Input D D D Q Q Q

Clock Clock Clock

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PARALLEL LOAD SHIFT REGISTERS

• Some shift registers have the ability for you to load all their flip- flops at once, i.e. in parallel. Q1 Q2 Q3 Qn

Serial in Serial out

FF1 FF2 FF3 …….. FFn

Serial clock

Parallel load clock

// in 1 // in 2 // in 3 // in n

• Doing this then allows you to “clock out” each bit in turn (starting with bit n) using the serial clock. This gives parallel-to-serial conversion. (// is a common abbreviation for "parallel“)

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SHIFT LEFT SHIFT REGISTERS

• The shift registers shown so far shift data to the right. A simple rewiring gives a shift register that can move data left. Of course these may also have the ability to parallel load. Q1 Q2 Q3 Serial in

D in D in D in

FF1 FF2 FF3

Serial clock

Parallel clock // in // in // in

1 2 3

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SHIFT REGISTERS AND MATHS

• As well as serialising and de-serialising data (parallel to serial, serial to parallel), shift registers have other purposes.
• Shifting a binary number left one place multiplies it by 2.
• Shifting a +ve binary number right one place divides it by 2.
• Shifting left, shifting right, in addition to adding and complementing, allow us the perform the basic arithmetic operations – addition, subtraction, multiplication and division.
• Multiplication is performed as a series of shifts-left and adds.
• Division is performed as a series of shifts-right and subtractions.

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"LEFT" VS "RIGHT"

• What do we mean by a “shift-left register”?
• No matter which way we draw them, "left" should mean "from least significant bit position to most significant".
• Redrawing: Q7 Q6 Q5 Q0 Serial out Serial in

FF7 FF6 FF5 …….. FF0

Serial clock

Parallel load clock

// in // in // in // in

bit7 bit6 bit5 bit0

Here the serial transfer convention is “big end first”.

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THE COMPLETE SHIFT REGISTER.

• To perform all these actions a shift register may need to be able to shift left, shift right and parallel load. It may have three different clock inputs to perform these actions as shown.

Q3 Q2 Q1 Q0

Serial in SR Serial in SL

Serial out SL FF3 FF2 FF1 FF0 Serial out SR

SR clock (to all ff) SL clock (to all ff)

//-Load clock (to all ff) //-Load data inputs

The main register in an UART (universal asynchronous receiver/transmitter) is a shift register like this (except more than 4 bits long)

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WHERE ARE WE?

Fast memory (RAM) Persistent

• program and data memory (Disks)

Central processing Mother Programmable unit (CPU) board shift register registers

Screen memory ALU within Keyboard the CPU Input / Output accel

24 Channels cards Mouse

THINGS TO REMEMBER (FILL THIS IN)

Flip- Uses Inputs Clocked? Circuit Elements (Gates) Flop

RS

D

JK

T

IN THE LAB...

• Build an 8-bit adder.
• Build a bunch of Flip-Flops from gates
• Test them.